Oriol Roig
Departament d'Arquitectura de Computadors
Universitat Politècnica de Catalunya
I'm no longer here, but I still check my e-mail weekly.
Some publications
- Automatic Generation of Synchronous Test Patterns
for Asynchronous Circuits.
Oriol Roig, Jordi Cortadella, Marco A. Peñna and Enric Pastor
34th Design Automation Conference,
Anaheim, June 1997.
- Formal Verification and Testing of Asynchronous Circuits.
Oriol Roig.
Doctoral Thesis,
UPC/DAC, May 1997.
- Hierarchical Gate-Level Verification of Speed-Independent Circuits.
Oriol Roig, Jordi Cortadella and Enric Pastor.
2nd Working Conference on Asynchronous Design Methodologies,
London, May 1995.
- Verification of Asynchronous Circuits by BDD-based Model Checking of
Petri Nets.
Oriol Roig, Jordi Cortadella and Enric Pastor.
16th International Conference on Application and Theory
of Petri Nets,
Torino, Jun 1995.
Available CAD tools
- versify
- VERiFY a Speed-Independent circuit,
a Signal Transition Graph or
a Petri net.
- testify
- Automatic Test Pattern Generation for Asynchronous Circuits. (same link as versify)
Further information
Last updated and validated: Aug 2001